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188 lines
3.4 KiB
188 lines
3.4 KiB
14 years ago
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# Runtime support
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# Configurable parameters
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# Set PLL ratios - M=4, P=2, 58.9824 MHz clock
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.equ PLL_M, 4
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.equ PLL_P, 2
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.equ FLASHCLOCKS, 3 /* 40-60MHz clock */
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.equ APB_DIVIDER, 4 /* 1, 2 or 4 */
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.equ UND_STACK_SIZE, 0x0004
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.equ SVC_STACK_SIZE, 0x0004
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.equ ABT_STACK_SIZE, 0x0004
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.equ FIQ_STACK_SIZE, 0x0004
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.equ IRQ_STACK_SIZE, 0x0080
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.equ USR_STACK_SIZE, 0x0400
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# Processor definitions
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1b
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.equ Mode_SYS, 0x1f
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.equ I_Bit, 0x80
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.equ F_Bit, 0x40
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# Register definitions
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.equ MAM_BASE, 0xE01FC000
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.equ MAMCR, 0
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.equ MAMTIM, 4
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.equ PLL_BASE, 0xE01FC080
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.equ PLLCON, 0x00
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.equ PLLCFG, 0x04
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.equ PLLSTAT, 0x08
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.equ PLLFEED, 0x0c
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.equ PLLCON_PLLE, (1<<0)
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.equ PLLCON_PLLC, (1<<1)
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.equ PLLCFG_MSEL, (0x1F<<0)
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.equ PLLCFG_PSEL, (0x03<<5)
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.equ PLLSTAT_PLOCK, (1<<10)
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.equ APBDIV_BASE, 0xE01FC100
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.equ APBDIV, 0
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# True is -1 so we subtract values together.
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.equ PLL_LOG_P, (0-(PLL_P>1)-(PLL_P>2)-(PLL_P>4))
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.equ PLLCFG_VAL, (PLL_M-1) | (PLL_LOG_P << 5)
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# 1 => 1, 2 => 2, 4 => 0
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.equ APB_VAL, (APB_DIVIDER & 3)
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.text
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.global _startup
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.func _startup
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_startup:
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vectors:
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b reset_handler
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b undefined_handler
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b swi_handler
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b prefetch_abort_handler
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b data_abort_handler
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nop /* reserved */
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b irq_handler
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b fiq_handler
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reset_handler:
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# MAM and PLL setup
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ldr r1, =MAM_BASE
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ldr r2, =PLL_BASE
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mov r3, #0xAA
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mov r4, #0x55
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# Configure and Enable PLL
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mov r0, #PLLCFG_VAL
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str r0, [r2, #PLLCFG]
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mov r0, #PLLCON_PLLE
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str r0, [r2, #PLLCON]
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str r3, [r2, #PLLFEED]
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str r4, [r2, #PLLFEED]
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# Disable MAM until we turn on the PLL
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mov r0, #0 /* MAM disabled */
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str r0, [r1, #MAMCR]
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# Wait until PLL Locked
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lockwait:
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ldr r0, [r2, #PLLSTAT]
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ands r0, r0, #PLLSTAT_PLOCK
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beq lockwait
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# Switch to PLL Clock
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mov r0, #(PLLCON_PLLE | PLLCON_PLLC)
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str r0, [r2, #PLLCON]
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str r3, [r2, #PLLFEED]
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str r4, [r2, #PLLFEED]
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# Enable MAM and set up flash timing
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mov r0, #FLASHCLOCKS
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str r0, [r1, #MAMTIM]
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mov r0, #2 /* MAM fully enabled */
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str r0, [r1, #MAMCR]
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# Set APB divider
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ldr r1, =APBDIV_BASE
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mov r0, #APB_DIVIDER
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str r0, [r1, #APBDIV]
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# Relocate .data section (Copy from ROM to RAM)
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ldr r1, =_etext
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ldr r2, =_data
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ldr r3, =_edata
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lrel:
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cmp r2, r3
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ldrlo r0, [r1], #4
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strlo r0, [r2], #4
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blo lrel
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# Clear .bss section (Zero init)
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mov r0, #0
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ldr r1, =_bss_start
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ldr r2, =_bss_end
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lzi:
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cmp r1, r2
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strlo r0, [r1], #4
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blo lzi
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# Set up stacks
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ldr r0, =_stack_end
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msr CPSR_c, #Mode_UND|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #UND_STACK_SIZE
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msr CPSR_c, #Mode_ABT|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #ABT_STACK_SIZE
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msr CPSR_c, #Mode_FIQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #FIQ_STACK_SIZE
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msr CPSR_c, #Mode_IRQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #IRQ_STACK_SIZE
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msr CPSR_c, #Mode_SVC|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #SVC_STACK_SIZE
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msr CPSR_c, #Mode_USR
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mov sp, r0
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# Stack Limit (only when compiled with "-mapcs-stack-check")
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sub sl, sp, #USR_STACK_SIZE
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# Prepare to go!
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mov r0, #0
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mov r1, #0
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adr lr, __back
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b main
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# Undefined handlers can just spin for now
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undefined_handler:
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swi_handler:
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prefetch_abort_handler:
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data_abort_handler:
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irq_handler:
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fiq_handler:
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__back:
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b __back
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.endfunc
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.end
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