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282 lines
6.1 KiB
282 lines
6.1 KiB
#include "timer.h" |
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#include "interrupt.h" |
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#include "uart.h" |
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#include "event.h" |
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#define FP0XVAL (*((volatile unsigned int *) 0x3FFFC014)) |
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#define TIMER0BASE 0xE0004000 |
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#define TIMER1BASE 0xE0008000 |
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#define TIMER2BASE 0xE0070000 |
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#define TIMER3BASE 0xE0074000 |
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#define IR 0x00 |
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#define TCR 0x04 |
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#define TC 0x08 |
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#define PR 0x0c |
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#define PC 0x10 |
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#define MCR 0x14 |
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#define MR0 0x18 |
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#define MR1 0x1C |
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#define MR2 0x20 |
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#define MR3 0x24 |
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#define CCR 0x28 |
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#define CR0 0x2C |
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#define CR1 0x30 |
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#define CR2 0x34 |
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#define CR3 0x38 |
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#define EMR 0x3C |
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#define CTCR 0x70 |
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#define PWM 0x74 |
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#define TREG(x) (((volatile unsigned char *)TIMER0BASE)[x]) |
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#define TWREG(x) (((volatile unsigned int *)TIMER0BASE)[(x)/sizeof(unsigned int)]) |
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#define T1REG(x) (((volatile unsigned char *)TIMER1BASE)[x]) |
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#define T1WREG(x) (((volatile unsigned int *)TIMER1BASE)[(x)/sizeof(unsigned int)]) |
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#define T2REG(x) (((volatile unsigned char *)TIMER2BASE)[x]) |
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#define T2WREG(x) (((volatile unsigned int *)TIMER2BASE)[(x)/sizeof(unsigned int)]) |
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#define T3REG(x) (((volatile unsigned char *)TIMER3BASE)[x]) |
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#define T3WREG(x) (((volatile unsigned int *)TIMER3BASE)[(x)/sizeof(unsigned int)]) |
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#define TCR_ENABLE (1<<0) |
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#define TCR_RESET (1<<1) |
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#define MR0I (1<<0) |
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#define MR0R (1<<1) |
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#define MR0S (1<<2) |
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#define MR1I (1<<3) |
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#define MR1R (1<<4) |
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#define MR1S (1<<5) |
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#define MR2I (1<<6) |
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#define MR2R (1<<7) |
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#define MR2S (1<<8) |
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#define MR3I (1<<9) |
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#define MR3R (1<<10) |
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#define MR3S (1<<11) |
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volatile unsigned int timer0_rising[4]; |
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volatile unsigned int timer0_width[4]; |
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#ifdef TIMER_CPPM |
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volatile unsigned int timer0_cppm[8]; |
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volatile unsigned int timer0_cppm_chan = 0; |
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volatile unsigned int timer0_sync_timestamp; |
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#endif |
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unsigned int timer_map[] = {0, 1, 2, 3, 4, 5, 6, 7}; |
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void __attribute__((interrupt("IRQ"))) timer_interrupt_handler(void); |
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void __attribute__((interrupt("IRQ"))) timer0_interrupt_handler(void); |
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void timer_event_handler(void); |
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/* Timer 0 : Capture */ |
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/* Timer 1 : Output */ |
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/* Timer 2 : Output */ |
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/* Timer 3 : System */ |
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void init_timer(void) |
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{ |
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T3REG(TCR) = TCR_ENABLE | TCR_RESET; |
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T3REG(CTCR) = 0; /* Use PCLK */ |
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T3WREG(TC) = 0; |
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T3WREG(PR) = TIMER_PRESCALE; |
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T3WREG(PC) = 0; |
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T3REG(TCR) = TCR_ENABLE; |
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interrupt_register(TIMER0, timer0_interrupt_handler); |
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TREG(TCR) = TCR_ENABLE | TCR_RESET; |
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TREG(CTCR) = 0; /* Use PCLK */ |
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TWREG(TC) = 0; |
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TWREG(PR) = TIMER0_PRESCALE; |
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TWREG(PC) = 0; |
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TWREG(CCR) = 0x00000fff; |
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TREG(TCR) = TCR_ENABLE; |
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T2REG(TCR) = TCR_ENABLE | TCR_RESET; |
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T2REG(CTCR) = 0; /* Use PCLK */ |
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T2WREG(PR) = 3; // Prescaling |
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T2WREG(PC) = 0; // Reset the prescale counter |
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T2WREG(TC) = 0; // Reset the counter |
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T2WREG(MCR) = 0x0400; // Reset on MR3 match |
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T2WREG(PWM) = 0x00000005; // Enable PWMs |
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T2WREG(MR3) = PWM_PERIOD; // Period duration |
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/* This is chosen to be an invalid output. */ |
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T2WREG(MR2) = 1; // Pulse width |
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T2WREG(MR0) = 1; // Pulse width |
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T1REG(TCR) = TCR_ENABLE | TCR_RESET; |
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T1REG(CTCR) = 0; /* Use PCLK */ |
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T1WREG(PR) = 3; // Prescaling |
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T1WREG(PC) = 0; // Reset the prescale counter |
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T1WREG(TC) = 0; // Reset the counter |
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T1WREG(MCR) = 0x0400; // Reset on MR3 match |
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T1WREG(PWM) = 0x00000003; // Enable PWMs |
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T1WREG(MR3) = PWM_PERIOD; // Period duration |
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/* This is chosen to be an invalid output. */ |
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T1WREG(MR1) = 1; // Pulse width |
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T1WREG(MR0) = 1; // Pulse width |
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T2REG(TCR) = TCR_ENABLE; |
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T1REG(TCR) = TCR_ENABLE; |
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} |
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unsigned int timer_read(void) |
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{ |
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return TWREG(TC); |
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} |
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void timer_delay_clocks(unsigned int clocks) |
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{ |
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signed int time = TWREG(TC) + clocks; |
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while (((signed int) (time-TWREG(TC))) > 0); |
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} |
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void timer_set_period(unsigned int period) |
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{ |
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interrupt_register(TIMER3, timer_interrupt_handler); |
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T3WREG(MR0) = period-1; |
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T3WREG(MCR) = MR0I | MR0R; |
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T3WREG(TC) = 0; |
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} |
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void __attribute__((interrupt("IRQ"))) timer_interrupt_handler(void) |
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{ |
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unsigned int ir; |
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ir = T3REG(IR); |
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T3REG(IR) = ir; |
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if (ir & (1<<0)) { |
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/* Match channel 0 */ |
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event_set(EVENT_TIMER); |
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} |
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interrupt_clear(); |
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} |
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void __attribute__((interrupt("IRQ"))) timer0_interrupt_handler(void) |
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{ |
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unsigned int ir; |
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unsigned int gpio; |
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ir = TREG(IR); |
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TREG(IR) = ir; |
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gpio = FP0XVAL; |
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if (ir & (1<<5)) { |
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/* Capture channel 1 */ |
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if (gpio & (1<<4)) { |
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timer0_rising[0] = TWREG(CR1); |
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} else { |
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timer0_width[0] = TWREG(CR1) - timer0_rising[0]; |
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#ifdef TIMER_CPPM |
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if (timer0_width[0] > TIMER_CPPM_SYNC) { |
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timer0_cppm_chan = 0; |
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timer0_sync_timestamp = timer0_rising[0]; |
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} else { |
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if (timer0_cppm_chan < 8) { |
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timer0_cppm[timer0_cppm_chan] = |
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timer0_width[0]; |
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timer0_cppm_chan++; |
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} |
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} |
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#endif |
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} |
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} |
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if (ir & (1<<6)) { |
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/* Capture channel 2 */ |
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if (gpio & (1<<6)) { |
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timer0_rising[1] = TWREG(CR2); |
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} else { |
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timer0_width[1] = TWREG(CR2) - timer0_rising[1]; |
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} |
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} |
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interrupt_clear(); |
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} |
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bool timer_valid(int channel) { |
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channel = TIMER_CH(channel); |
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/* Be careful here to ensure that this can't be in the past */ |
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unsigned int chtime = timer0_rising[channel]; /* Atomic */ |
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unsigned int time = TWREG(TC); /* Atomic */ |
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return (time - chtime) < TIMER_INPUT_TIMEOUT; |
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} |
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#ifdef TIMER_CPPM |
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bool timer_allvalid(void) { |
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/* Be careful here to ensure that this can't be in the past */ |
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unsigned int chtime = timer0_sync_timestamp; /* Atomic */ |
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unsigned int time = TWREG(TC); /* Atomic */ |
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return (time - chtime) < TIMER_INPUT_TIMEOUT; |
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} |
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#else |
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bool timer_allvalid(void) { |
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unsigned int time; |
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unsigned int chtime[4]; |
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int i; |
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/* Be careful here to ensure that this can't be in the past */ |
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for (i = 0; i < 4; i++) |
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chtime[i] = timer0_rising[i]; |
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time = TWREG(TC); |
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for (i = 0; i < 4; i++) |
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if ((time - chtime[i]) >= TIMER_INPUT_TIMEOUT) |
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return FALSE; |
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return TRUE; |
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} |
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#endif |
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void timer_set_pwm_value(int channel, int value) |
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{ |
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value = PWM_PERIOD - (PWM_MAX + value); |
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switch (channel) { |
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case 0: |
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T2WREG(MR2) = value; |
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break; |
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case 1: |
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T2WREG(MR0) = value; |
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break; |
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case 2: |
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T1WREG(MR0) = value; |
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break; |
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case 3: |
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T1WREG(MR1) = value; |
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break; |
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} |
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} |
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void timer_set_pwm_invalid(int channel) |
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{ |
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int value = 1; |
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switch (channel) { |
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case 0: |
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T2WREG(MR2) = value; |
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break; |
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case 1: |
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T2WREG(MR0) = value; |
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break; |
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case 2: |
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T1WREG(MR0) = value; |
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break; |
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case 3: |
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T1WREG(MR1) = value; |
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break; |
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} |
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} |
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